When fabricating an integrated circuit, it is important that each patterned layer be aligned with the previously formed layer or layers, at least within some permissible tolerance. For example, to align the various layers, a substrate having a photoresist applied thereon is placed in a photolithographic chamber, such as a “stepper” or “scanner.” A mask or reticle is then used to pattern the photoresist. As the patterned photoresist ultimately dictates the positioning of the underlying circuit layer to be etched, its alignment is critical.
To bring the substrate into alignment with the mask, an image of some structure on the mask and some structure on the wafer are compared using optical analysis equipment, for example. If alignment is needed, the optical analysis equipment can control the lateral and/or rotational positioning of the substrate. Such alignment is usually assessed at numerous locations around the substrate's perimeter, which accordingly requires reference to a plurality of alignment marks on the substrate.
Although alignment structures can constitute a portion of the circuit being fabricated, a dedicated structure separate from the circuit and known as an alignment mark is usually formed for this purpose. Such alignment marks are typically formed outside of the active integrated circuit area on the wafer, such as in the area in which the substrate will be scribed or “diced” for later insertion into packages.
However, such alignment marks may become covered with opaque materials during later processing steps, making them difficult to detect with the optical analysis equipment. Accordingly, the prior art has experimented with the use of backside alignment marks, which are located on the opposite side of the substrate from the front side where the active circuitry is formed. However, with existing backside alignment marks, extreme care must be taken to protect the near-perfectly smooth front side of the substrate. Moreover, existing backside alignment marks require extensive preparation (e.g., protective layer formation, photoresist deposition, patterning and removal, etching, removal of these layers, etc.) before processing of the circuit on the front of the substrate can begin in earnest.